As transistor manufacturing delves into the sub micron and deep submicron range (less than 0.25 microns), the short channel length of the transistors so formed causes an effect named, appropriately enough, the short channel effect. Raised source/drain junctions can provide shallow junctions with low series resistance and that reduce the short channel effect. Raised isolation regions increase the electrical isolation between adjacent transistors and, for example, reduces undesired leakage current.
U.S. Pat. No. 5,915,183 to Gambino et al. describes a process for forming raised source/drain junctions using chemical-mechanical polishing (CMP) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by salicide gate conductors and raised shallow isolation trench regions (STI).
U.S. Pat. No. 5,682,055 to Huang et al. describes a method of forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed therefrom.
U.S. Pat. No. 5,827,768 to Lin et al. describes a method of manufacturing a MOS (metal-oxide-semiconductor) transistor applied in the deep micron process. A polysilicon layer is mainly used to form a raised source/drain structure and self-alignment is achieved by means of a planarization process.